JSS Device Intel4004 CPU

This device simulates an Intel 4004 CPU. The real Intel 4004 used different signals for RAM bank specification, ROM selection, and addressing. For simplicity, the simulated CPU combines those signals into a "virtual" address. The source code contains a comment related to this, which is also reproduced here:


	// address
	//    4-bit MODE | 3-bit RAM | 1-bit ROM | 12-bit address => total 20-bit
	//    MODE: 0x8=DATA | 0x4=PROM | 0x2=RAM | 0x1=ROM
	//
	// ROM bank 0 = 0x10000
	// ROM bank 1 = 0x11000
	//
	// RAM bank 0 = 0x20000
	// RAM bank 1 = 0x21000
	//
	// PROM bank 0 = 0x40000
	// PROM bank 1 = 0x41000
	//
	// DATA bank 0 = 0x80000
	// DATA bank 1 = 0x82000
	// DATA bank 2 = 0x84000
	// DATA bank 3 = 0x88000
	// DATA bank 4 = 0x86000
	// DATA bank 5 = 0x8A000
	// DATA bank 6 = 0x8C000
	// DATA bank 7 = 0x8E000
	
	// ROM I/O = 0x10000 | SRC
	//      0x10000, 0x10010, 0x10020, 0x10030
	//      0x100E0 => enable/disable RAM write
	// DATA bank 0 /O = 0x80000 | SRC
	//		0x80000, 0x80010, 0x80020, 0x80030
	// DATA bank 1 /O = 0x82000 | SRC
	// DATA bank 2 /O = 0x84000 | SRC
	// DATA bank 3 /O = 0x88000 | SRC
	// DATA bank 4 /O = 0x86000 | SRC
	// DATA bank 5 /O = 0x8A000 | SRC
	// DATA bank 6 /O = 0x8C000 | SRC
	// DATA bank 7 /O = 0x8E000 | SRC
	// ROM 0  = 0x10000 | SRC
	// ROM 1  = 0x10010 not connected
	// ROM 2  = 0x10020 | SRC
	// ROM 3  = 0x10030 | SRC

Options

breakpoints - Address list (comma separated) for breakpoints. When a breakpoint is reached, the simulation will be automatically paused.

Device Connections

attachToDataBus - Allows attaching to a data bus for accessing data or controlling the data bus.
attachToControlBus - Allows attaching to a control bus for sending and reading signals, with associated data.

Implementation

https://github.com/ComputingMongoose/JavaSystemSimulator/blob/main/src/jss/devices/cpu/impl/Intel4004.java

Example configuration


{
	"name":"CPU",
	"type":"Intel4004",
	"configuration":[]
}

Example simulation